ADLINK CPCI-7300 32-CH 80 MB/s High-Speed Digital I/O Module

ADLINK CPCI-7300 32-CH 80 MB/s High-Speed Digital I/O Module

Key Features

Not recommended to be used in the system with greater than 2GB memory

Supports handshaking DIO transfer mode

On-board programmable timer pacer clock for clocked DIO

Scatter-gather DMA

On-board 32k words FIFO

Up to 80MB/s transfer ra

Features

■ x1 lane PCI Express® Interface (PCIe-7300A)

■ Supports a 32-Bit 5 V PCI bus (PCI-7300A)

■ 3U Eurocard form factor, CompactPCI compliant

■Not recommended to be used in the system with

greater than 2GB memory (cPCI-7300/PCI-7300A)

(PICMG 2.0 R2.1) (cPCI-7300)

■ 32-CH 5 V/TTL digital inputs/outputs

■ 20 MHz (80 MB/s) maximum transfer rate

■ 8. 16. or 32-Bit transfers

■ 4 auxiliary DI & 4 auxiliary DO

■Onboard 64 kB FIFO

■Onboard programmable timer pacer clock

■ Timed digital input sampling controlled by internal

timer or external clock

■ Independent trigger signals to start data

acquisition and pattern generation

CPCI-7300

■ Scatter-gather DMA

■ Supports handshaking digital I/O transfer mode

■ Repeated digital pattern generation from FIFO

■ Active terminators for high-speed and longdistance

data transfer

■ Supported Operating System

•Windows 7/8 x64/x86. Linux

■ Driver and SDK

•LabVIEW, MATLAB, C/C++, Visual Basic,

Visual Studio.NET

■ Software Utility

•AD-Logger

PCI/PCIe-7300A, cPCI-7300

32-CH 80 MB/s High-Speed  Digital I/O Cards

Specifications

Digital I/O

■Numbers of channel (Software configurable)

•16 DI & 16 DO

•32 DI

•32 DO

■Compatibility: 5 V/TTL

■Digital logic levels

•Input high voltage: 2-5.25 V

•Input low voltage: 0-0.8 V

•Output high voltage: 2.7 V minimum

•Output low voltage: 0.5 V maximum

■ Input load

•Terminator OFF- Input high current: 1 mA- Input low current: 20 mA

•Terminator ON- Termination resistor: 111 Ω- Termination voltage: 2.9 V- Input high current: 1 mA- Input low current: 22.4 mA

■Output driving capacity

•Source current: 8 mA

•Sink current: 48 mA

Transfer characteristics

■Data transfers:

Bus-mastering DMA with Scatter/Gather

■Data width: 32/16/8 Bit (programmable)

Data transfer count

■2 M double words (8 MB) for non-chaining

mode DMA

■No limitation for chaining mode (scatter/gather) DMA

Max transfer rate

■DO: 80 MBytes/s, 32-Bit output @ 20 MHz

DI: 80 MBytes/s, 32-Bit input @ 20 MHz

Trigger

■DI_TRG for digital inputs,

DO_TRG for digital outputs

■Compatibility: 5 V/TTL

■Trigger types: rising or falling edges

■Minimum pulse width: 32 ns

Clocking mode

■ Internal clock

•Internal clock sources: 20 MHz, 10 MHz, Timer#0

output (digital input pacer) and Timer #1

output (digital output pacer)

■External clock up to 40 MHz

■Handshaking

■Burst handshaking